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| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| |||||||||||||||||||||||||||||||||||||| real - time clock module ( 3 - wire interface ) 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 1 pt7c4302 features ? using external 32.768khz quartz crystal ? real - time clock (rtc) counts seconds, minutes hours, date of the month, month, day of the week, and year with leap - year compensation valid up to 2099 ? 31 - byte, nonvolatile (nv) ram for data storage ? time keep ing voltage: 1.5v to 5.5v ? uses less than 300na at 2.0v ? simple 3 - wire interface ? serial i/o for minimum pin count ? burst mode for reading/writing successive addresses in clock/ram ? ttl - compatible (vcc = 5v) ? optional industrial temperature range: - 40c to +85c ? battery backup ? trickle charger on chip for rechargeable energy source backup description the pt7c43 02 serial real - time clock is a low - power clock/calendar with a programmable square - wave output and 31 bytes of nonvolatile ram. address and data are tr ansferred serially via a 3 - wire bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour format with am/pm indicator. table 1 shows the basic functions of pt7c43 02 . more details are shown in section: overview of functions. p in assignment p in description pi n no. pin type description 1 vcc 2 p primary power. when v cc2 is greater than v cc1 + 0.2v, v cc2 will power the ic . while v cc2 ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 3 p t7c4302 real - time clock module ( 3 - wire interface ) dc electrical characteristics unless otherwise specified, gnd =0v, t a = 25 c, oscillation frequency = 32.768 khz. sym item pin condition s min typ max unit v cc 1 backup p ower voltage v cc1 - 1.5 - 5.5 v v cc 2 timing and r am data maintaining v cc2 - 1.2 - 5.5 v timing data writing voltage - 1.5 - 5.5 timing data reading voltage - 1.5 - 5.5 ram data writing voltage - 3.0 - 5.5 ram data reading voltage - 1.5 - 5.5 i cc1 current consumption v cc1 osc on, note 2, 5 v cc1 : 2 v - - 0.4 ma v cc1 : 5 v - - 1.2 osc on, note 1, 5 v cc1 : 2 v - 0.5 - ? cc1 : 5 v - 1 - osc off, note 4, 5 , 7 v cc1 : 2 v - 100 - na v cc1 : 5 v - 100 - i cc2 current consumption v cc2 osc on, note 2, 6 v cc1 : 2 v - - 0.425 ma v c c1 : 5 v - - 1.28 osc on, note 1, 6 v cc1 : 2 v - - 25.3 ? cc1 : 5 v - - 81 osc off, note 4, 6 v cc1 : 2 v - - 25 ? cc1 : 5 v - - 80 v il 1 low - level input voltage scl, /rst v cc1 : 5 v - 1.1 0.8 v v cc1 : 2 v - 0.6 0.4 v ih 1 high - level input vo ltage scl, /rst v cc1 : 5 v 2.0 1.3 - v v cc1 : 2 v 1.4 0.9 - v il 2 low - level input voltage x1 v cc1 : 5 v - 1.9 0.8 v v cc1 : 2 v - 0.9 0.6 v ih 2 high - level input voltage x1 v cc1 : 5 v 2.0 1.9 - v v cc1 : 2 v 1.4 0.9 - v o l low - level output voltage i/o i oh = 1.5ma, v cc = 2v - 0.08 0.4 v i oh = 4.0ma, v cc = 5v - 0.11 0.4 v oh high - level output voltage i/o i oh = - 0.4ma, v cc = 2v 1.6 1.9 - v i oh = - 1.0ma, v cc = 5v 2.4 4.9 - i il input leakage current /rst, sclk note 3 - - 500 ? oz output current wh en off i/o note 3 - - 500 ? td trickle charge diode voltage drop - - - 0.7 - v r1 trickle charge resistors - - - 2 - k ? note : 1. i/o open, /rst set to a logic 0, and /eosc bit = 0 (oscillator enabled). 2. i/o pin open, /rst high, sclk=2mhz at v cc = 5v; sclk = 500khz, v cc = 2.0v, and /eosc bit = 0 (oscillator enabled). 3. /rst, sclk, and i/o all have 40k ? pull - down resistors to ground. 4. /rst, i/o, and sclk open. the /eosc bit = 1 (oscillator disabled). 5. v cc2 = 0v. 6. v cc1 = 0v. 7. typi cal values are at 25 ? c. ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 4 p t7c4302 real - time clock module ( 3 - wire interface ) ac electrical characteristics figure 6 a timing diagram: read data transfer figure 6 b timing diagram: write data transfer t a = - 40 c to +85 c. unless otherwise specified. paramet er sym min typ max unit notes data to clk setup t dc v cc =2.0v 200 - - ns 1 v cc =5 .0 v 50 - - clk to data hold t cdh v cc =2.0v 280 - - ns 1 v cc =5 .0 v 70 - - clk to data delay t cdd v cc =2.0v - - 800 ns 1,2,3 v cc =5 .0 v - - 200 clk low time t cl v cc =2.0v 1000 - - ns 1 v cc =5 .0 v 250 - - clk high time t ch v cc =2.0v 1000 - - ns 1 v cc =5 .0 v 250 - - clk frequency t clk v cc =2.0v - - 0.5 m hz 1 v cc =5 .0 v 0 - 2.0 clk rise and fall t r ,t f v cc =2.0v - - 2000 ns 1 v cc =5 .0 v - - 500 rst to clk s etup t cc v cc =2.0v 4 - - ? s 1 v cc =5 .0 v 1 - - clk to rst hold t cch v cc =2.0v 240 - - ns 1 v cc =5 .0 v 60 - - rst inactive time t cwh v cc =2.0v 4 - - ? s 1 v cc =5 .0 v 1 - - rst to i/o high - z t cdz v cc =2.0v - - 280 ns 1 v cc =5 .0 v - - 70 sclk to i/o high - z t ccz v cc =2.0v - - 280 ns 1 v cc =5 .0 v - - 70 note : 1. measured at v ih = 2.0v or v il = 0.8v and 10ns maximum rise and fall time. 2. measured at v oh = 2.4v or v ol = 0.4v. 3. load capacitance = 50pf. ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 5 p t7c4302 real - time clock module ( 3 - wire interface ) recommended layout for crystal b uilt - in capacitors specifications and recommended external capacitors parameter symbol typ unit build - in capacitors x1 to gnd c g 11 pf x2 to gnd c d 11 pf recommended external capacitors for crystal c l =12.5pf x1 to gnd c 1 12 pf x2 to gnd c 2 12 pf r ecommended external capacitors for crystal c l =6pf x1 to gnd c 1 0 pf x2 to gnd c 2 0 pf note : the frequency of crystal can be optimized by external capacitor c 1 and c 2 , for frequency= 32.768 khz , c 1 and c 2 should meet the equation as below : cpar + [(c 1 +c g )*(c 2 +c d )]/ [(c 1 +c g )+(c 2 +c d )] =c l cpar is all parasitical capacitor between x1 and x2. c l is crystal s load capacitance. crystal specifications parameter symbol min typ max unit nominal frequency f o - 32.768 - khz series resistance esr - - 70 k ? l - 6/12.5 - pf note : the crystal, traces and crystal input pins should be isolated from rf generating signals. ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 6 p t7c4302 real - time clock module ( 3 - wire interface ) function description overview of functions 1. clock function cpu can read or write data including the year (last two digits), month, date, day, hour, minute, and second. any (two - digit) year that is a multiple of 4 is tre ated as a leap year and calculated automatically as such until the year 2099. 2. interface with cpu simple 3 - wire interface. 3. oscillator enable/disable oscillator can be enabled or disable by /eosc bit. but time count chain does not shut down when the bit is logic 1. 4. charger function the function is controlled by trickle charge register. customer can select the charge current by select the number of diode a nd resistor value through the register. for example: assume that a system power supply of 5v is appl ied to vcc2 and a super cap is connected to vcc1. also assume that the trickle charger has been enabled with one diode and resistor r1 between vcc2 and vcc1. the maximum current imax would, therefore, be calculated as follows: i max = (5.0v - diode drop)/r1 _ (5.0v - 0.7v) / 2k? _ 2.2ma as the super cap charges, the voltage drop between vcc1 and vcc2 will decrease and, therefore, the charge current will decrease. ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 7 p t7c4302 real - time clock module ( 3 - wire interface ) registers 1. allocation of registers addr. (hex) *1 function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 seconds (00 - 59) /eosc *2 s40 s20 s10 s8 s4 s2 s1 01 minutes (00 - 59) 0 m40 m20 m10 m8 m4 m2 m1 02 hours (00 - 23 / 01 - 12) 12, /24 0 h20 or p /a h10 h8 h4 h2 h1 03 dates (01 - 31) 0 0 d20 d10 d8 d4 d2 d 1 04 months (01 - 12) 0 0 0 mo10 mo8 mo4 mo2 mo1 05 days of the week (01 - 07) 0 0 0 0 0 w4 w2 w1 06 years (00 - 99) y80 y40 y20 y10 y8 y4 y2 y1 07 control wp *3 0 0 0 0 0 0 0 08 trickle charger tcs *4 tcs tcs tcs ds *5 ds rs *6 rs 1f clock burst *7 - - - - - - - - 20~3e ram *9 - - - - - - - - 3f ram burst *8 - - - - - - - - caution points: *1. pt7c4302 uses 5 bits for address. its address byte consists of 1 + ram/clock select bit +5 - bit addr. + read/write select bit. *2. oscillator enable bit. when thi s bit is set to 1, oscillator is stopped but time count chain is still active. *3. wp: write protect bit. wp bit should be cleared before attempting to write to the device. *4. tcs: trickle charger select. *5. ds: diode select. *6. rs: resistor se lect. *7. clock burst register address is used as clock/calendar burst mode operation address for consecutively read/write 0~7h registers. clock/calendar burst mode operation can continuously read 0h to maximum 7h registers in order; write 0~7h register s in order. less or larger than 8 bytes in clock burst write mode are ignored. *8. ram burst register address is used as ram burst mode operation address for consecutively read/write 20~3eh ram. less than 31 bytes in ram burst read/write mode are valid. * 9. pt7c4302 has 31 ? 8 static ram for customer use. it is volatile ram. *10. all bits marked with " 0 " are read - only bits. their value when read is always "0". all bits marked with " - " are customer using space. ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 8 p t7c4302 real - time clock module ( 3 - wire interface ) 2. control and status register addr. (hex) d escription d7 d6 d5 d4 d3 d2 d1 d0 07 control wp 0 0 0 0 0 0 0 (default) 0 0 0 0 0 0 0 0 wp: write protect bit. wp data description read / write 0 write operation is enabled. default 1 prevent a write operation to any other register. 3. time counter time digit display (in bcd code): ? second digits: range from 00 to 59 and carried to minute digits when incremented from 59 to 00. ? minute digits: range from 00 to 59 and carried to hour digits when incremented from 59 to 00. ? hour digits: see description on the /12, 24 bit. carried to day and day - of - the - week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 00 seconds /eosc * s40 s20 s10 s8 s4 s2 s1 (default) 0 undefined undefined undefined undefin ed undefined undefined undefined 01 minutes 0 m40 m20 m10 m8 m4 m2 m1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 02 hours 12, /24 0 h20 or p,/a h10 h8 h4 h2 h1 (default) undefined 0 undefined undefined undefined undefined undefined undefined * note: /eosc bit must be written into 0 to start the time count . a) 12 / 24 bit this bit is used to select between 12 - hour clock operation and 24 - hour clock operation. 12, /24 description hours register 0 24 - hour time displ ay 1 12 - hour time display be sure to select between 12 - hour and 24 - hour clock operation before writing the time data. 24 - hour clock 12 - hour clock 24 - hour clock 12 - hour clock 00 92 ( am 12 ) 12 b2 ( pm 12 ) 01 81 ( am 01 ) 13 a1 ( pm 01 ) 02 82 ( am 02 ) 14 a2 ( pm 02 ) 03 83 ( am 03 ) 15 a3 ( pm 03 ) 04 84 ( am 04 ) 16 a4 ( pm 04 ) 05 85 ( am 05 ) 17 a5 ( pm 05 ) 06 86 ( am 06 ) 18 a6 ( pm 06 ) 07 87 ( am 07 ) 19 a7 ( pm 07 ) 08 88 ( am 08 ) 20 a8 ( pm 08 ) 09 89 ( am 09 ) 21 a9 ( pm 09 ) 10 90 ( am 10 ) 22 b0 ( pm 10 ) 11 91 ( am 11 ) 23 b1 ( pm 11 ) ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 9 p t7c4302 real - time clock module ( 3 - wire interface ) 4. days of the week counter the day counter is a divide - by - 7 counter that counts from 01 to 07 and up 07 before starting again from 01. values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 05 day s of the week 0 0 0 0 0 w4 w2 w1 (default) 0 0 0 0 0 undefined undefined undefined 5. calendar counter the data format is bcd format. ? day digits: range from 1 to 31 (for january, march, may, july, august, october and december). range from 1 to 30 (for april, june, september and november ). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digit s when cycled to 1 . ? month digits: range from 1 to 12 and carried to year digits when cycl ed to 1. ? year digits: range from 00 to 99 and 00, 04, 08, , 92 and 96 are counted as leap years. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 03 dates 0 0 d20 d10 d8 d4 d2 d1 (default) 0 0 undefined undefined undefined undefined undefined undefined 04 months 0 0 0 m10 m8 m4 m2 m1 (default) 0 0 0 undefined undefined undefined undefined undefined 06 years y80 y40 y20 y10 y8 y4 y2 y1 (default) undefined undefined undefined undefined undefined undefined undefined undefined note: any registered im aginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction. 6. trickle charger addr. description d7 d6 d5 d4 d3 d2 d1 d0 8 trickle charger tcs tcs tcs tcs ds ds rs rs (default) 0 1 0 1 1 1 0 0 ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 10 p t7c4302 real - time clock module ( 3 - wire interface ) a) tr ickle charger select control the selection of the trickle charger. tcs data description read/ write other patent disable the trickle charger * default 0101 1010 enable the trickle charger b) diode select select whether one diode or two diodes are connect ed between vcc2 and vcc1. ds data description read/ write 00 or 11 the trickle charger is disabled independently of tcs. * default 01 one diode is selected. 10 two diodes are selected. c) resistor select select whether one diode or two diodes are conne cted between vcc2 and vcc1. rs data description read/ write 00 no resistor. * default 01 r1 with typ. 2k ? ? ? communication 1. 3 - wire interface a) command byte figure 1 command byte the command byte is shown in f igure 1. each data transfer is initiated by a command byte. the msb (bit 7) must be a logic 1. if it is 0, writes to the pt7c4302 will be disabled. bit 6 specifies clock/calendar data if logic 0 or ram data if logic 1. bits 1 through 5 specify the designat ed registers to be input or output, and the lsb (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. the command byte is always input starting with the lsb (bit 0). b) rst and scl signal all data transfers are i nitiated by driving the rst input high and terminated by driving the rst input low. a clock cycle is a sequence of a falling edge followed by a rising edge. for data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. if the rst input is low all data transfer terminates and the sda pin goes to a high impedance state. data transfer is illustrated in figure 2 and figure 3 . at power - up, rst must be a logic 0 until vcc > 2.0v. also sclk must be a t a logic 0 when rst is driven to a logic 1 state. ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 11 p t7c4302 real - time clock module ( 3 - wire interface ) c) single byte read figure 2 single byte read following the eight sclk cycles that input a read command byte, a data byte is output on the falling edge of the next eight s clk cycles. note that the firs t data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. additional sclk cycles will transmit the same data bytes by pt7c4302 so long as rst remains high. this operation permits continuous burst mode read capability. also, the sda pin is tri - stated upon each rising edge of sclk. data is output starting with bit 0. d) single byte write figure 3 signal byte write following the eight sclk cycles that input a write command byte, a data byte is input on th e rising edge of the next eight sclk cycles. additional sclk cycles are ignored. data is input starting with bit 0. e) burst mode burst mode is specified for either the clock/calendar or the ram registers by addressing location 31 decimal (address bits: a 4 a 3 a2 a1 a0 = 1 1 1 1 1 showed in fig ure 1 ). as before, bit 6 specifies clock or ram and bit 0 specifies read or write. there is no data storage capacity at locations 9 through 31 in the clock/calendar registers or location 31 in the ram registers. reads or writes in burst mode start with bit 0 of address 0. when writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. if the number of transferred bytes is less than eight, the data will be ignored. however, when writing to ram in burst mode , it is not necessary to write all 31 bytes for the data to transfer. each byte that is written will be transferred to ram regardless of whether all 31 bytes are written or not. additional sclk cyc les are ignored. ? clock/calendar burst mode the clock/calendar command byte specifies burst mode operation. in this mode the first eight clock/calendar registers can be consecutively read or written starting with bit 0 of address 0. if the write protect bi t is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). the trickle charger is not accessible in burst mode. at the beginning of a cl ock burst read, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re - read the registers in case of an update of the ma in registers during a read. ? ram burst mode the ram command byte specifies burst mode operation. in this mode, the 31 ram registers can be consecutively read or written starting with bit 0 of address 0. note: pt7c4302 use 94h, 96h as test mode address. cus tomer should not use the address . ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 12 p t7c4302 real - time clock module ( 3 - wire interface ) mechanical information we (8 - pin soic) min max a 1.350 1.750 a1 0.100 0.250 a2 1.350 1.550 b 0.330 0.510 c 0.170 0.250 d 4.700 5.100 e 3.800 4.000 e1 5.800 6.200 e l 0.400 1.270 0 8 symbol dimensions in millimeters 1.27 bsc note: 1) controlling dimensions in millimeters. 2) ref : jedec ms - 012e/aa ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 13 p t7c4302 real - time clock module ( 3 - wire interface ) z e e (lead free and green 8 - pin t dfn) symbol min. max a 0.700 0.800 a1 0.000 0.500 a3 d 1.924 2.076 e 2.924 3.076 d1 1.400 1.600 e1 1.400 1.600 k b 0.200 0.300 e l 0.224 0.376 pkg. dimensions(mm) 0.203ref 0.200min 0.500typ note: ref: jedec mo-229 ||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2 015 - 11 - 000 4 pt0225 - 6 11 / 2 5 /1 5 14 p t7c4302 real - time clock module ( 3 - wire interface ) ordering information part number package code package pt7c43 02 w e w lead f ree and green 8 - pin soic ( w ) PT7C4302WEx w lead free and green 8 - pin soic (w) tape/reel pt7c43 02 ze e ze lead free and green 8 - pin tdfn ( ze ) pt7c43 02 ze ex ze lead free and green 8 - pin tdfn ( ze ) tape/reel notes: ? e = pb - free and green ? adding x suffix = tape /r ee l pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or perfor mance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom |
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